Power And Timing Modeling, Optimization and Simulation (PATMOS), Sep 2013
Karlsruhe, Allemagne
H Ye, L Lacassagne, J Falcou, D Etiemble, L Cabaret, O Florent
Texte intégral

High Level Synthesis for Systems on Chip is a challenging way to cut off development time, while assuming a good level of performance. But the HLS tools are limited by the abstraction level of the description to perform some high level transforms.This paper evaluates the impact of such high level transforms for ASICs. We have evaluated recursive and non recursive filters for signal processing an morphological filters for image processing. We show that the impact of HLTs to reduce energy consumption is high : from ×3.4 for one 1D filter up to ×5.6 for cascaded 1D filters and about ×3.5 for morphological 2D filters.