Design and Architectures for Signal and Image Processing (DASIP), Oct 2012
Ye H., Lacassagne L., Etiemble D., Cabaret L., Falcou J., Romero A., Florent O
High Level Synthesis for System on Chip is a challenging way to cut off development time, while assuming a good level of performance. But the HLS tools are limited by the abstraction level of the description to perform some high level transforms. This paper evaluates the impact of such high level transforms for ASICs and softcores on FPGA. On the repre sentative example of motion detection, we show that we have a speedup of ×1.5 for a softcore on FPGA and ×2.5 for an ASIC while the energy is divided by a factor ×2.90 for the ASIC.